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CodeGen: Simplify UNM_NUM/UNM_VEC lowering

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vxorpd has a 3-argument form but the lowering is written assuming we are
targeting SSE. Since we aren't, we can directly vxorpd into the target
register.
This commit is contained in:
Arseny Kapoulkine 2024-02-26 15:06:57 -08:00
parent c9324853e5
commit b4a4053ad0
1 changed files with 2 additions and 23 deletions
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25
CodeGen/src/IrLoweringX64.cpp
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@ -541,18 +541,7 @@ void IrLoweringX64::lowerInst(IrInst& inst, uint32_t index, const IrBlock& next)
{
inst.regX64 = regs.allocRegOrReuse(SizeX64::xmmword, index, {inst.a});
RegisterX64 src = regOp(inst.a);
if (inst.regX64 == src)
{
build.vxorpd(inst.regX64, inst.regX64, build.f64(-0.0));
}
else
{
build.vmovsd(inst.regX64, src, src);
build.vxorpd(inst.regX64, inst.regX64, build.f64(-0.0));
}
build.vxorpd(inst.regX64, regOp(inst.a), build.f64(-0.0));
break;
}
case IrCmd::FLOOR_NUM:
@ -664,17 +653,7 @@ void IrLoweringX64::lowerInst(IrInst& inst, uint32_t index, const IrBlock& next)
{
inst.regX64 = regs.allocRegOrReuse(SizeX64::xmmword, index, {inst.a});
RegisterX64 src = regOp(inst.a);
if (inst.regX64 == src)
{
build.vxorpd(inst.regX64, inst.regX64, build.f32x4(-0.0, -0.0, -0.0, -0.0));
}
else
{
build.vmovsd(inst.regX64, src, src);
build.vxorpd(inst.regX64, inst.regX64, build.f32x4(-0.0, -0.0, -0.0, -0.0));
}
build.vxorpd(inst.regX64, regOp(inst.a), build.f32x4(-0.0, -0.0, -0.0, -0.0));
if (!FFlag::LuauCodegenVectorTag)
build.vpinsrd(inst.regX64, inst.regX64, build.i32(LUA_TVECTOR), 3);