From b4a4053ad07881550405d2260e252dde1ea1d123 Mon Sep 17 00:00:00 2001 From: Arseny Kapoulkine Date: Mon, 26 Feb 2024 15:06:57 -0800 Subject: [PATCH] CodeGen: Simplify UNM_NUM/UNM_VEC lowering vxorpd has a 3-argument form but the lowering is written assuming we are targeting SSE. Since we aren't, we can directly vxorpd into the target register. --- CodeGen/src/IrLoweringX64.cpp | 25 ++----------------------- 1 file changed, 2 insertions(+), 23 deletions(-) diff --git a/CodeGen/src/IrLoweringX64.cpp b/CodeGen/src/IrLoweringX64.cpp index c5188dc4..24b61ed0 100644 --- a/CodeGen/src/IrLoweringX64.cpp +++ b/CodeGen/src/IrLoweringX64.cpp @@ -541,18 +541,7 @@ void IrLoweringX64::lowerInst(IrInst& inst, uint32_t index, const IrBlock& next) { inst.regX64 = regs.allocRegOrReuse(SizeX64::xmmword, index, {inst.a}); - RegisterX64 src = regOp(inst.a); - - if (inst.regX64 == src) - { - build.vxorpd(inst.regX64, inst.regX64, build.f64(-0.0)); - } - else - { - build.vmovsd(inst.regX64, src, src); - build.vxorpd(inst.regX64, inst.regX64, build.f64(-0.0)); - } - + build.vxorpd(inst.regX64, regOp(inst.a), build.f64(-0.0)); break; } case IrCmd::FLOOR_NUM: @@ -664,17 +653,7 @@ void IrLoweringX64::lowerInst(IrInst& inst, uint32_t index, const IrBlock& next) { inst.regX64 = regs.allocRegOrReuse(SizeX64::xmmword, index, {inst.a}); - RegisterX64 src = regOp(inst.a); - - if (inst.regX64 == src) - { - build.vxorpd(inst.regX64, inst.regX64, build.f32x4(-0.0, -0.0, -0.0, -0.0)); - } - else - { - build.vmovsd(inst.regX64, src, src); - build.vxorpd(inst.regX64, inst.regX64, build.f32x4(-0.0, -0.0, -0.0, -0.0)); - } + build.vxorpd(inst.regX64, regOp(inst.a), build.f32x4(-0.0, -0.0, -0.0, -0.0)); if (!FFlag::LuauCodegenVectorTag) build.vpinsrd(inst.regX64, inst.regX64, build.i32(LUA_TVECTOR), 3);