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https://github.com/luau-lang/luau.git
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292 lines
12 KiB
C++
292 lines
12 KiB
C++
// This file is part of the Luau programming language and is licensed under MIT License; see LICENSE.txt for details
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#pragma once
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#include "Luau/RegisterA64.h"
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#include "Luau/AddressA64.h"
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#include "Luau/ConditionA64.h"
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#include "Luau/Label.h"
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#include <string>
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#include <vector>
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namespace Luau
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{
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namespace CodeGen
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{
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namespace A64
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{
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enum FeaturesA64
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{
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Feature_JSCVT = 1 << 0,
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};
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class AssemblyBuilderA64
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{
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public:
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explicit AssemblyBuilderA64(bool logText, unsigned int features = 0);
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~AssemblyBuilderA64();
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// Moves
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void mov(RegisterA64 dst, RegisterA64 src);
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void mov(RegisterA64 dst, int src); // macro
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// Moves of 32-bit immediates get decomposed into one or more of these
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void movz(RegisterA64 dst, uint16_t src, int shift = 0);
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void movn(RegisterA64 dst, uint16_t src, int shift = 0);
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void movk(RegisterA64 dst, uint16_t src, int shift = 0);
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// Arithmetics
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void add(RegisterA64 dst, RegisterA64 src1, RegisterA64 src2, int shift = 0);
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void add(RegisterA64 dst, RegisterA64 src1, uint16_t src2);
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void sub(RegisterA64 dst, RegisterA64 src1, RegisterA64 src2, int shift = 0);
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void sub(RegisterA64 dst, RegisterA64 src1, uint16_t src2);
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void neg(RegisterA64 dst, RegisterA64 src);
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// Comparisons
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// Note: some arithmetic instructions also have versions that update flags (ADDS etc) but we aren't using them atm
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void cmp(RegisterA64 src1, RegisterA64 src2);
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void cmp(RegisterA64 src1, uint16_t src2);
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void csel(RegisterA64 dst, RegisterA64 src1, RegisterA64 src2, ConditionA64 cond);
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void cset(RegisterA64 dst, ConditionA64 cond);
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// Bitwise
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void and_(RegisterA64 dst, RegisterA64 src1, RegisterA64 src2, int shift = 0);
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void orr(RegisterA64 dst, RegisterA64 src1, RegisterA64 src2, int shift = 0);
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void eor(RegisterA64 dst, RegisterA64 src1, RegisterA64 src2, int shift = 0);
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void bic(RegisterA64 dst, RegisterA64 src1, RegisterA64 src2, int shift = 0);
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void tst(RegisterA64 src1, RegisterA64 src2, int shift = 0);
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void mvn_(RegisterA64 dst, RegisterA64 src);
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// Bitwise with immediate
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// Note: immediate must have a single contiguous sequence of 1 bits set of length 1..31
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void and_(RegisterA64 dst, RegisterA64 src1, uint32_t src2);
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void orr(RegisterA64 dst, RegisterA64 src1, uint32_t src2);
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void eor(RegisterA64 dst, RegisterA64 src1, uint32_t src2);
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void tst(RegisterA64 src1, uint32_t src2);
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// Shifts
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void lsl(RegisterA64 dst, RegisterA64 src1, RegisterA64 src2);
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void lsr(RegisterA64 dst, RegisterA64 src1, RegisterA64 src2);
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void asr(RegisterA64 dst, RegisterA64 src1, RegisterA64 src2);
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void ror(RegisterA64 dst, RegisterA64 src1, RegisterA64 src2);
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void clz(RegisterA64 dst, RegisterA64 src);
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void rbit(RegisterA64 dst, RegisterA64 src);
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void rev(RegisterA64 dst, RegisterA64 src);
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// Shifts with immediates
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// Note: immediate value must be in [0, 31] or [0, 63] range based on register type
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void lsl(RegisterA64 dst, RegisterA64 src1, uint8_t src2);
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void lsr(RegisterA64 dst, RegisterA64 src1, uint8_t src2);
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void asr(RegisterA64 dst, RegisterA64 src1, uint8_t src2);
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void ror(RegisterA64 dst, RegisterA64 src1, uint8_t src2);
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// Bitfields
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void ubfiz(RegisterA64 dst, RegisterA64 src, uint8_t f, uint8_t w);
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void ubfx(RegisterA64 dst, RegisterA64 src, uint8_t f, uint8_t w);
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void sbfiz(RegisterA64 dst, RegisterA64 src, uint8_t f, uint8_t w);
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void sbfx(RegisterA64 dst, RegisterA64 src, uint8_t f, uint8_t w);
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// Load
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// Note: paired loads are currently omitted for simplicity
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void ldr(RegisterA64 dst, AddressA64 src);
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void ldrb(RegisterA64 dst, AddressA64 src);
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void ldrh(RegisterA64 dst, AddressA64 src);
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void ldrsb(RegisterA64 dst, AddressA64 src);
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void ldrsh(RegisterA64 dst, AddressA64 src);
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void ldrsw(RegisterA64 dst, AddressA64 src);
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void ldp(RegisterA64 dst1, RegisterA64 dst2, AddressA64 src);
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// Store
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void str(RegisterA64 src, AddressA64 dst);
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void strb(RegisterA64 src, AddressA64 dst);
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void strh(RegisterA64 src, AddressA64 dst);
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void stp(RegisterA64 src1, RegisterA64 src2, AddressA64 dst);
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// Control flow
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void b(Label& label);
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void bl(Label& label);
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void br(RegisterA64 src);
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void blr(RegisterA64 src);
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void ret();
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// Conditional control flow
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void b(ConditionA64 cond, Label& label);
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void cbz(RegisterA64 src, Label& label);
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void cbnz(RegisterA64 src, Label& label);
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void tbz(RegisterA64 src, uint8_t bit, Label& label);
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void tbnz(RegisterA64 src, uint8_t bit, Label& label);
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// Address of embedded data
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void adr(RegisterA64 dst, const void* ptr, size_t size);
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void adr(RegisterA64 dst, uint64_t value);
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void adr(RegisterA64 dst, double value);
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// Address of code (label)
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void adr(RegisterA64 dst, Label& label);
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// Floating-point scalar moves
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// Note: constant must be compatible with immediate floating point moves (see isFmovSupported)
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void fmov(RegisterA64 dst, RegisterA64 src);
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void fmov(RegisterA64 dst, double src);
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// Floating-point scalar math
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void fabs(RegisterA64 dst, RegisterA64 src);
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void fadd(RegisterA64 dst, RegisterA64 src1, RegisterA64 src2);
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void fdiv(RegisterA64 dst, RegisterA64 src1, RegisterA64 src2);
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void fmul(RegisterA64 dst, RegisterA64 src1, RegisterA64 src2);
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void fneg(RegisterA64 dst, RegisterA64 src);
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void fsqrt(RegisterA64 dst, RegisterA64 src);
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void fsub(RegisterA64 dst, RegisterA64 src1, RegisterA64 src2);
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void ins_4s(RegisterA64 dst, RegisterA64 src, uint8_t index);
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void ins_4s(RegisterA64 dst, uint8_t dstIndex, RegisterA64 src, uint8_t srcIndex);
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void dup_4s(RegisterA64 dst, RegisterA64 src, uint8_t index);
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// Floating-point rounding and conversions
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void frinta(RegisterA64 dst, RegisterA64 src);
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void frintm(RegisterA64 dst, RegisterA64 src);
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void frintp(RegisterA64 dst, RegisterA64 src);
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void fcvt(RegisterA64 dst, RegisterA64 src);
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void fcvtzs(RegisterA64 dst, RegisterA64 src);
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void fcvtzu(RegisterA64 dst, RegisterA64 src);
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void scvtf(RegisterA64 dst, RegisterA64 src);
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void ucvtf(RegisterA64 dst, RegisterA64 src);
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// Floating-point conversion to integer using JS rules (wrap around 2^32) and set Z flag
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// note: this is part of ARM8.3 (JSCVT feature); support of this instruction needs to be checked at runtime
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void fjcvtzs(RegisterA64 dst, RegisterA64 src);
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// Floating-point comparisons
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void fcmp(RegisterA64 src1, RegisterA64 src2);
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void fcmpz(RegisterA64 src);
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void fcsel(RegisterA64 dst, RegisterA64 src1, RegisterA64 src2, ConditionA64 cond);
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void udf();
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// Run final checks
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bool finalize();
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// Places a label at current location and returns it
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Label setLabel();
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// Assigns label position to the current location
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void setLabel(Label& label);
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// Extracts code offset (in bytes) from label
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uint32_t getLabelOffset(const Label& label)
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{
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CODEGEN_ASSERT(label.location != ~0u);
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return label.location * 4;
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}
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void logAppend(const char* fmt, ...) LUAU_PRINTF_ATTR(2, 3);
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uint32_t getCodeSize() const;
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unsigned getInstructionCount() const;
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// Resulting data and code that need to be copied over one after the other
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// The *end* of 'data' has to be aligned to 16 bytes, this will also align 'code'
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std::vector<uint8_t> data;
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std::vector<uint32_t> code;
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std::string text;
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const bool logText = false;
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const unsigned int features = 0;
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// Maximum immediate argument to functions like add/sub/cmp
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static constexpr size_t kMaxImmediate = (1 << 12) - 1;
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// Check if immediate mode mask is supported for bitwise operations (and/or/xor)
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static bool isMaskSupported(uint32_t mask);
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// Check if fmov can be used to synthesize a constant
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static bool isFmovSupported(double value);
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private:
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// Instruction archetypes
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void place0(const char* name, uint32_t word);
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void placeSR3(const char* name, RegisterA64 dst, RegisterA64 src1, RegisterA64 src2, uint8_t op, int shift = 0, int N = 0);
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void placeSR2(const char* name, RegisterA64 dst, RegisterA64 src, uint8_t op, uint8_t op2 = 0);
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void placeR3(const char* name, RegisterA64 dst, RegisterA64 src1, RegisterA64 src2, uint8_t op, uint8_t op2);
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void placeR1(const char* name, RegisterA64 dst, RegisterA64 src, uint32_t op);
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void placeI12(const char* name, RegisterA64 dst, RegisterA64 src1, int src2, uint8_t op);
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void placeI16(const char* name, RegisterA64 dst, int src, uint8_t op, int shift = 0);
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void placeA(const char* name, RegisterA64 dst, AddressA64 src, uint16_t opsize, int sizelog);
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void placeB(const char* name, Label& label, uint8_t op);
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void placeBC(const char* name, Label& label, uint8_t op, uint8_t cond);
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void placeBCR(const char* name, Label& label, uint8_t op, RegisterA64 cond);
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void placeBR(const char* name, RegisterA64 src, uint32_t op);
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void placeBTR(const char* name, Label& label, uint8_t op, RegisterA64 cond, uint8_t bit);
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void placeADR(const char* name, RegisterA64 src, uint8_t op);
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void placeADR(const char* name, RegisterA64 src, uint8_t op, Label& label);
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void placeP(const char* name, RegisterA64 dst1, RegisterA64 dst2, AddressA64 src, uint8_t op, uint8_t opc, int sizelog);
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void placeCS(const char* name, RegisterA64 dst, RegisterA64 src1, RegisterA64 src2, ConditionA64 cond, uint8_t op, uint8_t opc, int invert = 0);
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void placeFCMP(const char* name, RegisterA64 src1, RegisterA64 src2, uint8_t op, uint8_t opc);
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void placeFMOV(const char* name, RegisterA64 dst, double src, uint32_t op);
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void placeBM(const char* name, RegisterA64 dst, RegisterA64 src1, uint32_t src2, uint8_t op);
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void placeBFM(const char* name, RegisterA64 dst, RegisterA64 src1, int src2, uint8_t op, int immr, int imms);
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void placeER(const char* name, RegisterA64 dst, RegisterA64 src1, RegisterA64 src2, uint8_t op, int shift);
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void placeVR(const char* name, RegisterA64 dst, RegisterA64 src1, RegisterA64 src2, uint16_t op, uint8_t op2);
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void place(uint32_t word);
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struct Patch
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{
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enum Kind
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{
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Imm26,
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Imm19,
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Imm14,
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};
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Kind kind : 2;
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uint32_t label : 30;
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uint32_t location;
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};
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void patchLabel(Label& label, Patch::Kind kind);
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void patchOffset(uint32_t location, int value, Patch::Kind kind);
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void commit();
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LUAU_NOINLINE void extend();
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// Data
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size_t allocateData(size_t size, size_t align);
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// Logging of assembly in text form
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LUAU_NOINLINE void log(const char* opcode);
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LUAU_NOINLINE void log(const char* opcode, RegisterA64 dst, RegisterA64 src1, RegisterA64 src2, int shift = 0);
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LUAU_NOINLINE void log(const char* opcode, RegisterA64 dst, RegisterA64 src1, int src2);
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LUAU_NOINLINE void log(const char* opcode, RegisterA64 dst, RegisterA64 src);
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LUAU_NOINLINE void log(const char* opcode, RegisterA64 dst, int src, int shift = 0);
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LUAU_NOINLINE void log(const char* opcode, RegisterA64 dst, double src);
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LUAU_NOINLINE void log(const char* opcode, RegisterA64 dst, AddressA64 src);
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LUAU_NOINLINE void log(const char* opcode, RegisterA64 dst1, RegisterA64 dst2, AddressA64 src);
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LUAU_NOINLINE void log(const char* opcode, RegisterA64 src, Label label, int imm = -1);
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LUAU_NOINLINE void log(const char* opcode, RegisterA64 src);
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LUAU_NOINLINE void log(const char* opcode, Label label);
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LUAU_NOINLINE void log(const char* opcode, RegisterA64 dst, RegisterA64 src1, RegisterA64 src2, ConditionA64 cond);
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LUAU_NOINLINE void log(Label label);
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LUAU_NOINLINE void log(RegisterA64 reg);
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LUAU_NOINLINE void log(AddressA64 addr);
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uint32_t nextLabel = 1;
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std::vector<Patch> pendingLabels;
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std::vector<uint32_t> labelLocations;
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bool finalized = false;
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bool overflowed = false;
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size_t dataPos = 0;
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uint32_t* codePos = nullptr;
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uint32_t* codeEnd = nullptr;
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};
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} // namespace A64
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} // namespace CodeGen
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} // namespace Luau
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